1. Related Applications
This Patent Application is related to co-pending patent application Ser. No. 07/999,387, filed Dec. 31, 1992, entitled "Apparatus for Transferring Information Between an Interrupt Producer and an Interrupt Service Environment", of James W. Alexander, which is assigned to Intel Corporation, the Assignee of the present application, and which is incorporated by reference herein.
2. Field of the Invention
The invention generally relates to integrated circuits such as microprocessors and microcontrollers and in particular to microprocessors and microcontrollers provided with a test control capability.
3. Description of Related Art
Microprocessor and microcontroller devices are commonly provided with interchip testing capability. One example is a test system adapted to the IEEE Joint Test Action Group (JTAG) test protocols identified as IEEE standard 1149.1. In such a system, a JTAG test device is connected to a pair of integrated chips or to a single chip. The JTAG device generates test commands for testing the chips. Input and output of JTAG test commands is achieved through a set of JTAG-dedicated pins provided on each chip to be tested. Typically, the JTAG test device is employed to perform a "boundary-scan test". The JTAG test commands are typically drawn from a fairly limited set of commands particularly adapted for testing the interconnections of integrated chips and are not typically well suited for testing or monitoring the internal logic of a chip. General information regarding boundary-scan test strategies and implementations may be found in "Boundary-Scan Test, A Practical Approach", by Harry Bleeker, Peter Van Den Eijnden and Frans de Jong, Kluwer Academic publishers 1993.
Many integrated chips are additionally provided with an on-chip test device adapted for providing test visibility onto the internal logic and functions of the chip. For example, the Intel family of microprocessor chips typically include an in-circuit emulator (ICE) for use in testing, debugging and monitoring the microprocessor chip. The ICE duplicates and imitates behavior of the chip by using programming techniques and special machine features which permit the ICE to execute microcode and assembly language written for the chip. An ICE monitor external to the chip generates ICE test input signals and receives and evaluates responsive test output signals. Initially, the ICE was employed only during development and debugging of the chip and was retained in the final commercial chip only to avoid the need to provide a second die for creating a chip having the ICE. Although initially retained solely as an artifact of the design and debugging process, more recently the ICE has been employed for performing in-circuit testing of the chip after fabrication. Access to the ICE is typically achieved with a set of ICE-dedicated pins provided on the microprocessor chip. The ICE-dedicated pins are unused during normal processor execution.
The provision of both boundary-scan type JTAG testing and in-circuit ICE testing allows for a fairly comprehensive set of test commands for testing and monitoring the microprocessor chip. However, the need to provide separate pins for JTAG access and for ICE access is undesirable, particularly for microprocessor chips having a large set of required pins wherein the additional pins for both ICE and JTAG testing cannot easily be accommodated. Moreover, there is some redundancy in on-chip circuitry required for processing both JTAG commands and ICE commands.
It would be desirable to provide a mechanism which reduces the number of separate JTAG and ICE pins and any redundant circuitry. However, ICE test commands are synchronized to a chip core clock signal, which may be clocked at 50-150 MHz or more. The JTAG test commands are generated at, and synchronized to, a JTAG clock rate, which is typically 12 MHz. As such, merging of the JTAG and ICE command functions is not straight-forward. Indeed, even if the JTAG commands were to be generated at the same frequency as the ICE commands, the JTAG commands would still not be synchronized with the chip clock signals. Indeed, the IEEE standard defining JTAG protocol specifically states that the JTAG clock may not be specified with respect to any other clock, especially a core clock.